PIC18F/LF1XK50
DS41350E-page 22
Preliminary
2010 Microchip Technology Inc.
2.6.1
OSCTUNE REGISTER
The HFINTOSC is factory calibrated, but can be
adjusted in software by writing to the TUN<5:0> bits of
the OSCTUNE register (Register 2-3).
The default value of the TUN<5:0> is ‘000000’. The
value is a 6-bit two’s complement number.
When
the
OSCTUNE
register
is
modified,
the
HFINTOSC frequency will begin shifting to the new
frequency. Code execution continues during this shift,
while giving no indication that the shift has occurred.
OSCTUNE does not affect the LFINTOSC frequency.
The operation of features that depend on the LFINTOSC
clock source frequency, such as the Power-up Timer
(PWRT), Watchdog Timer (WDT), Fail-Safe Clock Mon-
itor (FSCM) and peripherals, are not affected by the
change in frequency.
The OSCTUNE register also implements the INTSRC
and SPLLEN bits, which control certain features of the
internal oscillator block.
The INTSRC bit allows users to select which internal
oscillator provides the clock source when the 31 kHz
frequency option is selected. This is covered in greater
The SPLLEN bit controls the operation of the frequency
multiplier. For more details about the function of the
REGISTER 2-3:
OSCTUNE: OSCILLATOR TUNING REGISTER
R/W-0
INTSRC
SPLLEN
TUN5
TUN4
TUN3
TUN2
TUN1
TUN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
INTSRC: Internal Oscillator Low-Frequency Source Select bit
1
= 31.25 kHz device clock derived from 16 MHz HFINTOSC source (divide-by-512 enabled)
0
= 31 kHz device clock derived directly from LFINTOSC internal oscillator
bit 6
SPLLEN: Software Controlled Frequency Multiplier PLL bit
1
= PLL enabled (for HFINTOSC 8 MHz only)
0
= PLL disabled
bit 5-0
TUN<5:0>: Frequency Tuning bits
011111
= Maximum frequency
011110
=
000001
=
000000
= Oscillator module is running at the factory calibrated frequency.
111111
=
100000
= Minimum frequency
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